RXLIE=DISABLE, THREIE=DISABLE, ABTOINTEN=DISABLE, RBRIE=DISABLE, ABEOINTEN=DISABLE
Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. When DLAB=0.
| RBRIE | Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt. 0 (DISABLE): Disable the RDA interrupt. 1 (ENABLE): Enable the RDA interrupt. |
| THREIE | Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR[5]. 0 (DISABLE): Disable the THRE interrupt. 1 (ENABLE): Enable the THRE interrupt. |
| RXLIE | Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. 0 (DISABLE): Disable the RX line status interrupts. 1 (ENABLE): Enable the RX line status interrupts. |
| RESERVED | Reserved |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| RESERVED | Reserved |
| ABEOINTEN | Enables the end of auto-baud interrupt. 0 (DISABLE): Disable end of auto-baud Interrupt. 1 (ENABLE): Enable end of auto-baud Interrupt. |
| ABTOINTEN | Enables the auto-baud time-out interrupt. 0 (DISABLE): Disable auto-baud time-out Interrupt. 1 (ENABLE): Enable auto-baud time-out Interrupt. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |